FPGA Implementation of Phase Noise Equalization for High Speed 5G OFDM using Parallel Processing Algorithm

Abstract

Phase noise significantly degrades the system performance in high-speed 5G orthogonal frequency division multiplexing (OFDM) systems, particularly within the challenging FR2 band, which can support up to 400 MHz of bandwidth. As a result, efficient cancellation techniques for phase noise are necessary. This paper introduces an effective field-programmable gate array (FPGA) implementation for phase noise cancellation in 5G OFDM. To address the inherent limitations in FPGA clock speed at high data rates, parallel processing is employed. Additionally, a novel complex multiplication optimization is presented, which significantly reduces logic gate usage and enhances hardware efficiency compared to standard methods. The effectiveness of the proposed maximum likelihood estimation (MLE) based approach is confirmed through simulations and real-time testing on a Virtex-7 FPGA. The results show excellent agreement between simulation and hardware, with significant phase noise reduction and bit error rates (BER) below 10⁻³ for 16-QAM and 64-QAM, and 10⁻² for 256-QAM. The implementation is highly efficient, using only 3% of FPGA slices, demonstrating its practical feasibility for 5G FR2 deployments.