Improved Development Cycle for 8-bit FPGA-Based Soft-Macros Targeting Complex Algorithms

Authors

  • Ehsan Ali Chulalongkorn University
  • Wanchalerm Pora Chulalongkorn University

DOI:

https://doi.org/10.4186/ej.2021.25.12.21

Keywords:

FPGA, PicoBlaze, 8-bit soft microprocessor, software development methods, verification techniques

Abstract

Developing complex algorithms on 8-bit processors without proper development tools is challenging. This paper integrates a series of novel techniques to improve the development cycle for 8-bit soft-macros such as Xilinx PicoBlaze. The improvements proposed in this paper reduce development time significantly by eliminating the required resynthesis of the whole design upon HDL source code changes. Additionally, a technique is proposed to increase the maximum supported data memory size for PicoBlaze which facilitates development of complex algorithms. Also, a general verification technique is proposed based on a series of testbenches that perform code verification using comparison method. The proposed testbench scenario integrates “Inter-Processor Communication (IPC), shared memory, and interrupt” concepts that lays out a guideline for FPGA developers to verify their own designs using the proposed method. The proposed development cycle relies on a chip that has Programmable Logic (PL) fabric (to hold the soft processor) alongside of a hardened processor (to be used as algorithm verifier), therefore, a Xilinx Zynq Ultrascale+ MPSoC is chosen which has a hardened ARM processor. The development cycle proposed in this paper targets the PicoBlaze, but it can be easily ported to other FPGA macros such as Lattice Mico8, or any non-Xilinx FPGA macros.

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Author Biographies

Ehsan Ali

Department of Electrical Engineering, Faculty of Engineering, Chulalongkorn University, Bangkok, 10330, Thailand

Wanchalerm Pora

Department of Electrical Engineering, Faculty of Engineering, Chulalongkorn University, Bangkok, 10330, Thailand

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Published In
Vol 25 No 12, Dec 30, 2021
How to Cite
[1]
E. Ali and W. Pora, “Improved Development Cycle for 8-bit FPGA-Based Soft-Macros Targeting Complex Algorithms”, Eng. J., vol. 25, no. 12, pp. 21-35, Dec. 2021.

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